circuit note cn- 0109 circuit designs using an alog devices products apply these product pairings quickly and with confidence. for more information and/or support call 1 -800- analogd (1 -800-262- 5643) or visit www.analog.com/circuit . devices connected /reference d ad9958 / ad9858 500 msps/1 gsps direct digital synthesizer (dds) ad9515 clock distribution ic and pin programmable mini - divider ad6645 14- bit, 80 msps /105 msps adc low jitter sampling clock generator for high performance adcs using the ad9958/ad9858 500 msps/1gsps dds and ad9515 clock distribution ic rev. 0 circuits from the lab from analog devices have been designed and buil t by analog devices engineers. standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. however, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. accordingly, in no event shall analog devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any circuit from the lab . (continued on last page) one technology way, p.o. bo x 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 analog devices, inc. all rights reserved. circuit function and benefits this circuit uses a direct digital synthesizer (dds) with sub - hertz tuning resolution as a low jitter sampling clock source for high performance adcs. the ad9515 clock distribution ic provides pecl logic levels to the adc. ho wever, the ad9515 internal divider feature also allows the dds to run at a higher frequency into the ad9515 front end, effectively increasing input slew rate. a higher slew rate into the ad9515 input squaring circuit can help reduce broadband jitter in the clock path. jitter on the adc sampling clock produces degradation in the overall signal - to - noise ratio (snr ). the relationship is given by equation 1. ? ? ? ? ? ? ? ? = j ft snr 2 1 log 20 10 (1) where f is the full - scale analog input frequency, and t j is the rms jitter. "snr" in equation 1 is the snr due solely to clock jitter and does not depend on the resolution of the adc. the following data supports low jitter attainable from a dds in clocking applications. further details on eq uation 1 and its use for evaluating the jitter on adc sampling clocks can be found in application note an - 501. circuit description the cir cuit configuration in figure 1 shows a dds - based clock generator, consisting of a dds followed by a reconstruction filter and an ad9515 clock distribution ic, used to provide the sampling clock for an analog - to - digital converter ( adc). the dds sampling clock is derived from a rohde and schwarz sma signal generator. the jitter measurement was made by using the clock derived from the dds and the ad9515 as the sampling clock for the high performance ad6645 14 - bit, 80 msps/105 msps ad c. the analog input signal for the a dc is a filtered 170.3 mhz sine wave derived from a low jitter wenzel crystal oscillator ( www.wenzel.com ). data was taken on two different dds es: the ad9958 (500 msps) and the ad98 58 (1 gsps). 08396-001 ad6645 fft analysis bpf rohde and schwarz sma generator 500mhz and 1ghz @ +6dbm reconstruction filter ain = 170.3mhz differential pecl sampling clock wenzel uln-series crystal oscillator ad9515 lpf/bpf dds ad9958, ad9858 figure 1. dds - b ased adc sampling clock generator (simplified diagram) by evaluating the contribution of the adcs differential non - linearity and thermal noise and then applying the dds - based clock and measuring the adc snr, the added jitter attributable to the dds - based clock can be derived. for more details on the measurement setup and the jitter calculations, refer to application note an - 823. also, application note an - 837 is instructive for designing dac reconstruction filters with optimal stop - band performance. table 1 shows data for the ad9958 test results. the data confirms that better jitter performance is achieved as the frequency, or slew rate, of the dds output frequency is increased an d as the dd s output filter pass band is decreased. table 2 shows the ad9858 with a 5% band - pass filter, a 225 mhz low - pass filter, and various levels of dds output power. as expected, lower jitter is achieved as power is inc reased and bandwidth reduced. with a 5% band - pass filter, the majority of the spurs from the dac are attenuated. the jitter in this case is much more dependent on noise coupling between the dac output and the limiter input. this is proven by the strong cor relation between jitter reduction and increased
cn- 0109 circuit note rev. 0 | page 2 of 3 slew rate. note that rms jitter values consistently less than 1 ps can be achieved using the ad9858 circuit. these circuits must be constructed on multilayer pc boards with large area ground planes using pr oper grounding, layout, and decoupling techniques (see mt - 031 tutorial, grounding data converters and solving the mystery of agnd and dgnd and mt - 101 tutorial, decoupli ng te chni ques ) in order to achieve these performance levels. consult the evaluation board documentation for the ad9958, ad9858, ad9515, and ad6645 for more guidance. table 1 . jitter response of ad9958 and ad9515 vs. f out , power, frequency , and filter bw table 2 . jitter response of ad9858 and ad9515 vs. f out , power, frequency , and filter bw product dds sa m ple r ate (mhz) dds output fre quency (mhz) dds ou t put power (dbm) dds reconstru c tion filter (mhz) ad9515 d ivider output s e t ting ad9515 output fre quency (mhz) jitter (rms) (ps) ad9958 /ad9515 500 38.88 ? 3.6 200 lpf 1 38.88 4.1 ad9958 /ad9515 500 38.88 ? 3.6 200 lpf 2 19.44 4.1 ad9958 /ad9515 500 38.88 ? 4.7 47 lpf 1 38.88 2.4 ad9958 /ad9515 500 38.88 ? 4.7 47 lpf 2 19.44 2.4 ad9958 /ad9515 500 38.88 ? 3.3 5% bpf 1 38.88 1.5 ad9958 /ad9515 500 38.88 ? 3.3 5% bpf 2 19.44 1.5 ad9958 /ad9515 500 77.76 ? 3.8 200 lpf 1 77.76 2.5 ad9958 /ad9515 500 77.76 ? 3.8 200 lpf 2, 4 38.88, 19.44 2.5 ad9958 /ad9515 500 77.76 ? 4.9 85 lpf 1 77.76 1.5 ad9958 /ad9515 500 77.76 ? 4.9 85 lpf 2, 4 38.88, 19.44 1.5 ad9958 /ad9515 500 77.76 ? 3.8 5% bpf 1 77.76 1.1 ad9958 /ad9515 500 77.76 ? 3.8 5% bpf 2, 4 38.88, 19.44 1.1 ad9958 /ad9515 500 155.52 ? 5.5 200 lpf 2 77.76 1.5 ad9958 /ad9515 500 155.52 ? 5.5 200 lpf 4, 8 38.88, 19.44 1.5 ad9958 /ad9515 500 155.52 ? 5.6 5% bpf 2 77.76 0.68 a d9958 /ad9515 500 155.52 ? 5.6 5% bpf 4, 8 38.88, 19.44 0.68 product dds sa m ple r ate (mhz) dds output fre quency (mhz) dds ou t put power (dbm) dds reconstru c tion filter (mhz) ad9515 d ivider output s e t ting ad9515 output fre quency (mhz) jitter (rms) (ps) ad9858/ad9515 1000 155.52 +7.7 225 lpf 2 77.76 0.56 ad9858/ad9515 1000 155.52 +7.7 225 lpf 4,8 38.88, 19.44 0.56 ad9858/ad9515 1000 155.52 +7.7 5% bpf 2 77.76 0.33 ad9858/ad9515 1000 155.52 +7.7 5% bpf 4, 8 38.88, 19.44 0.33 ad9858/ad9515 1000 155.52 +2.6 225 lpf 2 77.76 0.63 ad9858/ad9515 1000 155.52 +2.6 225 lpf 4, 8 38.88, 19.44 0.63 ad9858/ad9515 1000 155.52 +1.1 5% bpf 2 77.76 0.42 ad985 8 /ad9515 1000 155.52 +1.1 5% bpf 4, 8 38.88, 19.44 0.42 ad9858/ad9515 1000 155.52 ? 3.2 225 lpf 2 77.76 0.73 ad9858/ad9515 1000 155.52 ? 3.2 225 lpf 4, 8 38.88, 19.44 0.73 ad9858/ad9515 1000 155.52 ? 4.6 5% bpf 2 77.76 0.64 ad9858/ad9515 1000 155.52 ? 4.6 5% bpf 4, 8 38.88, 19.44 0.64
circuit note cn- 0109 rev. 0 | page 3 of 3 c ommon variations anal og devices offers a variety of direct digital synthesizer, c lock distribution chips , and clock b uffers to build a dds - based clock generator. refer to www.anal og.com/dds and www.analog.com/clock for more information. learn more an - 501 application note, a perture uncertainty and adc system performance . analog devices. an - 823 application no te, direct digital synthesizers in clocking applications . analog devices. an - 837 application note, dds - based clock jitter performance vs. dac reconstruction filter performance . analog devices. kester, walt. 2005. the data conversion handbook . analog devices. chapters 6 and 7. kester, walt. 2006. high speed system applications . analog devices. chapter 2, optimizing data converter interfaces. kester, walt. 2006. high speed system applications . analog devices. chapter 3, dacs, ddss, plls, and clock distribution. mt - 031 tutorial, grounding data converters and solving the mystery of agnd and dgnd . analog devices. mt - 101 tutorial, decoupling techniques . analog devices. data sheets and evaluation boards ad6645 data sheet. ad9515 data sheet. ad9858 data sheet. ad9958 data sheet. ad6645 evaluation board . ad9515 evaluatio n board . ad9858 evaluation board . ad9958 evaluation board . revision history 7 /09 revision 0 : initial version (continued from first page) "circuits from the lab" are intended only for use with analog devices products and are the intellectual property of analog devices or its licensors. while you may use the "circuits from the lab" in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the "circuits fr om the lab". information furnished by analog devices is believed to be accurate and reliable. however, "circuits from the lab " are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implie d warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by analog devices for their use, nor for any infringements of patents or other rights of third parties that may result from t heir use. analo g devices reserves the right to change any "circuits from the lab" at any time without notice, but is under no obligation to do so. trademarks and registered trademarks are the p roperty of their respective owners. ? 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. cn08396 - 0 - 7/09(0)
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